Arria 10® FPGAs and SoCs deliver the highest performance at 20 nm offering a one speed-grade performance advantage over competing devices. Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPs).
- One speed grade faster than competing FPGAs and SoCs
- The industry’s only midrange 28.3 Gbps support
- Highest performance 2,666 Mbps DDR4 SDRAM memory interface
- IEEE 754-compliant hard floating-point with 1,500 GFLOPS of DSP performance
- 96 transceiver lanes deliver 3.6 Tbps of serial bandwidth
Up to 40 Percent Lower Power Than the Previous-Generation FPGAs and SoCs
- Programmable Power Technology – Reduce device power in lower performance circuits while also delivering highest performance where needed
- Smart voltage ID – Operate devices to run optimum lower voltage without impacting performance
- VCC power manager – Operate devices at multiple voltage levels for either higher performance or lower power
- Low static power grades – Select devices with lower maximum static power
Industry’s Only 20 nm ARM-Based SoC
- Multiple SoC choices with dual-core ARM® Cortex®-A9 MPCore™hard processor system (HPS)
- 1.5 GHz CPU operation per core
- Move existing Arria V SoC designs in 28 nm to Arria 10 SoC with no changes to processor code
- Learn more about the Arria 10 SoC
Save Board Space with Integration
- 2X more density versus the previous generation midrange with over 1 million logic elements (LEs)
- Hard intellectual property (IP) cores: DDR4 memory controllers and PCI Express® (PCIe®) 3.0 specification (Gen3)
- Enpirion® PowerSoCs offer customers the smallest footprint, highest performance, lower system power, higher reliability and efficiency, and faster time-to-market to power Arria 10 FPGAs and SoCs
Increase Productivity and Decrease Time to Market with Altera’s Quartus II Software
- Industry’s fastest compile time at 20 nm and most advanced design environment
- Best-in-class IP cores including 100G Ethernet, 100G Interlaken, and PCIe Gen3, with 2X performance and lower latency
- Industry-leading compile times using this software release (an average of 2.5X faster than the nearest competitor’s software), enabling faster design iterations and faster timing closure
- C-based design entry using the Altera® SDK for OpenCL™, offering a design environment that is easy to implement on FPGAs
- System-level design environment with Qsys system integration tool
- DSP Builder – a model-based DSP environment within the MATLAB/Simulink environment
The Arria 10 FPGAs and SoCs are ideal for a broad array of applications such as wireless, wireline, military, broadcast, and other end markets.
Arria 10 FPGA Signal Integrity Kit
This kit enables a thorough evaluation of transceiver signal integrity and device interoperability. Features include five full-duplex 28 gigabits per second (Gbps) transceiver channels with edge launch connectors, one 14 Gbps backplane connector (from Amphenol), and ten full-duplex 12.5 Gbps transceiver channel with Samtec Bullseye connector. This board also includes several programmable clock oscillators, user push buttons, dual in-line package (DIP) switches, user LEDs, a 7-segment LCD display, power and temperature measurement circuitry, Ethernet, an embedded USB-BlasterTM II, and JTAG interfaces.
Arria 10 FPGA Signal Integrity Kit Block Diagram
Arria 10 FPGA Development Kit
This kit provides a full-featured hardware development platform for prototyping and testing high-speed serial interfaces to an Arria 10 GX FPGA. This kit includes the PCI Express® (PCIe®) x8 form factor, two FMC connectors for expandability, Ethernet, USB, and serial digital interfaces (SDIs). The board includes one connector for plugging in DRAM and SRAM daughtercards. Supported daughtercard formats include DDR4 x72 SDRAM, DDR3 x72 SDRAM, RLDRAM 3 x36, and QDR IV x36 SRAM. This board also includes SMA connectors for transceiver output, clock output, and clock input. Several programmable oscillators are available and other user interfaces include user push buttons, DIP switches, bi-color user LEDs, an LCD display, power, and temperature measurement circuitry.
Arria 10 FPGA Development Kit Block Diagram
Arria 10 FPGAs & SoCs Address a Wide Range of Applications
Altera's Arria® 10 FPGAs and SoCs deliver over 60% higher performance and up to 40% lower power compared to prior-generation midrange FPGAs, as well as up to 15% higher performance and up to 60% lower power compared to prior-generation high-end FPGAs. With a high-performance logic fabric and transceiver performance of up to 28.05 Gbps for chip-to-chip and chip-to-module interfaces as well as backplane support up to 17.4 Gbps, Arria 10 FPGAs and SoCs deliver the integration needed to address a wide range of applications for many industries, including communications, defense, broadcast, high-performance computing, test, and medical.
Wireless Backhaul Applications
The balance of high-performance and low-power capabilities of Arria 10 FPGAs and SoCs is ideally suited for wireless base stations, mobile backhaul, and remote radio head designs. With a comprehensive set of power reduction features, Arria 10 FPGAs and SoCs reduce power by up to 40% compared to prior-generation midrange devices. The Arria 10 FPGA's core performance of over 500 MHz enables 5X oversampling to provide users 100 MHz of RF bandwidth. By offering higher numbers of variable-precision digital signal processing (DSP) blocks and dual-core ARM® Cortex®-A9 processor options, along with support for Common Public Radio Interface (CPRI), small form factor pluggable (SFP), and JESD protocols, Arria 10 FPGAs and SoCs are low-risk design alternatives to application-specific integrated circuits. They have the added benefit of adaptability and reprogrammability to accommodate emerging and evolving protocols.
Learn more about Altera support for wireless communications applications
Wireless Backhaul Block Diagram
10x10G Optical Transport
As 100G transmission equipment becomes more widely deployed, Arria 10 FPGAs and SoCs provide a path to lower power and system cost. In addition, the up to 53 Mb of embedded RAM, hard silcon IP for 10G/40G-BASEKR forward error correction (FEC), and broad support for Gigabit Ethernet (GbE) protocols and Interlaken, as well as SoC options for Arria 10 devices provide tools to distinguish your product features in the areas of switching, security, monitoring, self-test, and traffic and policy management.
Learn more about Altera support for wireline communications applications
10x10G Optical Transport Block Diagram
Military RADAR/FlexDAR
Initiatives from Naval Research Lab and other sources are seeking out new ways to develop flexible, multi-mission RADAR, or 'FlexDAR' capabilities. Arria 10 FPGAs and SoCs provide the power and programmability options necessary for FlexDAR design. Secure communications, avionics, and navigation system designs are also ideal for implementation in Arria 10 FPGAs and SoCs. These applications will benefit from lower power, high transceiver channel count, over 3,000 multipliers, as well as faster and more advanced variable-precision DSP blocks and SoC capabilities. Users also benefit from productivity enhancing design development options like DSP Builder and support for Open Computing Language (OpenCLTM).
Learn more about Altera support for military applications
Military RADAR/FlexDAR Block Diagram
Broadcast and Professional Audio-Visual Equipment
Arria 10 FPGA offers the most power-, space-, and cost-efficient integration of video and image processing including 4K, 3D, and CODECs for the shortest time-to-market for production studio equipment. The generous embedded memory and external memory bandwidth support 4K and 3D processing, and high transceiver counts support management and processing up to 96 full rate channels, or 72 independent channels of 10G serial digital interface (SDI).
Learn more about Altera support for broadcast applications
Broadcast and Professional Audio-Visual Equipment Block Diagram
Additional End Markets
For more information on how to use the Altera® FPGAs and SoCs in other applications, refer to the following pages:
Fonte - Altera
